VHDL 2008/93/87 simulator

An abstraction library for interfacing EDA tools

Repurposing existing HDL tools to help writing better code

SPI master and SPI slave for FPGA written in VHDL

A Python package to use FPGA development tools programmatically.

PCIe (1.0a to 2.0) Virtual Root Complex model, in C, co-simulating with Verilog, SystemVerilog and VHDL, with Endpoint capabilities

Simple UART controller for FPGA written in VHDL

♻️ Convert the NEORV32 processor into a synthesizable plain-Verilog netlist module using GHDL.

📁 NEORV32 projects and exemplary setups for various FPGAs, boards and (open-source) toolchains.

A JSON library implemented in VHDL.

Examples of using PSL for functional and formal verification of VHDL with GHDL (and SymbiYosys)

IP Core Library - Published and maintained by the Open Source VHDL Group

My own FPGA architecture simulated in VHDL, realized with 7400-logic on PCB.

Scripts to build and use docker images including GHDL

Trying to verify Verilog/VHDL designs with formal methods and tools

Virtual development board for HDL design

cryptography ip-cores in vhdl / verilog

A simple CPU in VHDL for educational purposes

✔️ Port of RISCOF to check NEORV32 for RISC-V ISA compatibility.

USB virtual model in C++, co-simulating with Verilog, SystemVerilog and VHDL